Mar
22
Programm Committee Members of the VIII Jornadas de Computación Empotrada y Reconfigurable (JCER’24)
March 22, 2024 | Comments Off on Programm Committee Members of the VIII Jornadas de Computación Empotrada y Reconfigurable (JCER’24)
Joaquín Gracia-Morán and Juan C. Ruiz-García will serve as members of the Programm Committee of the VIII Jornadas de Computación Empotrada y Reconfigurable (JCER’24), that will be held in A Coruña next June.
Mar
6
9th International Workshop on Safety and Security of Intelligent Vehicles
March 6, 2023 | Comments Off on 9th International Workshop on Safety and Security of Intelligent Vehicles
David de Andrés is part of the Programm Committee of the 9th International Workshop on Safety and Security of Intelligent Vehicles. This workshop, co-located with DSN 2023, will be celebrated in Porto (Portugal), June 26, 2023.
Oct
4
Keynote speech at EDCC 2022
October 4, 2022 | Comments Off on Keynote speech at EDCC 2022
Juan Carlos Ruiz-García has given the Keynote Speech entitled “Reconfigurable logic for automotive edge computing: from promises to dependability assessment challenges” inside the Critical Automotive applications: Robustness & Safety (CARS) workshop, at EDCC 2022.
Sep
28
Session chair at Jornadas SARTECO 2022
September 28, 2022 | Comments Off on Session chair at Jornadas SARTECO 2022
Last wednesday (September 21st), Joaquín Gracia-Moran has chaired the Fault Tolerant Session at Jornadas SARTECO. Papers included were: “Estudio académico de la Fiabilidad de diferentes propuestas de Tolerancia a Fallos para el desarrollo de prácticas docentes”, Rafael Ayllón Gavilán, José Manuel Palomares Muñoz and Joaquín Olivares“Simulador Web de Sistemas Tolerantes a Fallos”, Antonio Gómez López, […]
Sep
5
Keynote speech at EDCC 2022
September 5, 2022 | Comments Off on Keynote speech at EDCC 2022
Juan Carlos Ruiz-García has been invited by the EDCC 2022 Steering Committe to give a Keynote Speech entitled “Reconfigurable logic for automotive edge computing: from promises to dependability assessment challenges”, inside the Critical Automotive applications: Robustness & Safety (CARS) workshop. Abstract: Reconfigurable logic devices have provided means to meet the requirements of evolution existing in […]
Jul
15
Paper presented at ITACA-WIICT 2022 (II)
July 15, 2022 | Comments Off on Paper presented at ITACA-WIICT 2022 (II)
The paper entitled “Analysis of overheads caused by adding Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, P.Martín-Tabares, C. Martínez-Ruiz and L.J. Saiz-Adalid has been presented at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Jul
15
Paper presented at ITACA-WIICT 2022 (I)
July 15, 2022 | Comments Off on Paper presented at ITACA-WIICT 2022 (I)
The paper entitled “Tolerating Double and Triple Random Errors with Low Redundancy Error Correction Codes”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás and P.J. Gil-Vicente has been presented at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Jun
29
Paper accepted at ITACA-WIICT 2022 (II)
June 29, 2022 | Comments Off on Paper accepted at ITACA-WIICT 2022 (II)
The paper entitled “Analysis of overheads caused by adding Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, P.Martín-Tabares, C. Martínez-Ruiz and L.J. Saiz-Adalid has been accepted at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). Abstract Nowadays, CMOS technology integration scale has allowed memory systems with a large storage capacity. […]
Jun
29
Paper accepted at ITACA-WIICT 2022 (I)
June 29, 2022 | Comments Off on Paper accepted at ITACA-WIICT 2022 (I)
The paper entitled “Tolerating Double and Triple Random Errors with Low Redundancy Error Correction Codes”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás and P.J. Gil-Vicente has been accepted at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). Abstract With the continuous size reduction of CMOS technology, faults suffered by […]
Jun
27
Paper accepted at Jornadas SARTECO 2022 (II)
June 27, 2022 | Comments Off on Paper accepted at Jornadas SARTECO 2022 (II)
The paper entitled “Evaluación de un Microprocesador RISC con capacidad de tolerancia a fallos” written by J. Gracia-Morán, J.C. Baraza-Calvo, D. Gil-Tomás, P.J. Gil-Vicente and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2022. Abstract Con la continua reducción de tamaño de la tecnología CMOS, la probabilidad de sufrir tanto fallos simples como múltiples en […]