Dependable-enough FPGA-Accelerated DNNs for Automotive Systems

Research goals:

Study the effect of faults on the different elements of FPGA-accelerated DNNs (convolution operators, pooling operators, fully connected layers, etc. implemented on LUTs, flip-flops, switch blocks, etc.), to define related fault models and failure modes.

Define novel and efficient fault injection methodologies to enable the dependability assessment of FPGA-accelerated DNNs to detect existing weaknesses, and verify developed fault mitigation strategies, especially those based on run-time reconfiguration.

Design new fault tolerance strategies, including those related to the run-time reconfiguration of the target device, and/or adapt deployed optimisations to mitigate detected weakness.

Design new strategies to compare and optimise implemented DNNs and fault tolerance mechanisms, according to multiple criteria, and paying especial attention to monitoring and triggering mechanisms that enable their dynamic deployment at run time.

Technological goals:

Develop/Adapt tools to support dependability assessment and verification processes.

Develop new tools to support the dynamic and automatic deployment of adaptive fault tolerance mechanisms on reconfigurable logic.

Develop/Adapt tools to enable dependability benchmarking and design space exploration to tune, at run-time, hardware accelerated DNNs according to operational conditions.

Design and implement a prototype platform to act as a demonstrator for the different technologies and tools developed within the project.

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