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The paper entitled “In-Memory Zero-Space Floating-Point-based CNN protection using non-significant and invariant bits”, and written by Juan Carlos Ruiz Garcia, Luis Jose Saiz-Adalid, David de Andrés Martínez, and Joaquín Gracia-Morán has been accepted at SAFECOMP 2024. Abstract Convolutional Neural Networks (CNNs) have accomplished significant success in various domains, including transportation, health care and banking. Millions […]

The paper entitled “Tolerancia a fallos múltiples en redes convolucionales en coma flotante de 16 bitsutilizando códigos correctores de errores” written by J.C. Ruiz-García, D. Andrés-Martínez, L.J. Saiz-Adalid, and J. Gracia-Morán has been accepted at Jornadas SARTECO 2024. Abstract Multitud de sistemas utilizan redes convolucionales para identificar objetos en las imágenes que analizan. Este análisis […]

The paper entitled “Estudio de la confiabilidad de una red neuronal convolucional cuantizada” written by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Ruiz-García, and D. Andrés-Martínez has been accepted at Jornadas SARTECO 2024. Abstract A medida que el uso de las redes neuronales se generaliza, el interés por su confiabilidad también aumenta. En concreto, las redes neuronales […]

The paper entitled “Protección mediante Códigos de Corrección de Errores de los pesos de una Red Neuronal implementada en Arduino” written by J. Gracia-Morán and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2024. Abstract Últimamente, el amplio uso de las redes neuronales ha provocado que éstas estén presentes en multitud de entornos, como pueden […]

The paper entitled “Zero-Space In-Weight and In-Bias Protection for Floating-Point-based CNNs”, written by Juan Carlos Ruiz, David de Andrés, Luis José Saiz-Adalid and Joaquín Gracia-Morán has been accepted at 19th European Dependable Computing Conference (EDCC), that will be held in Leuven (Belgium) next april. Abstract Deploying convolutional neural networks (CNNs) in image classification systems requires […]

J.C. Ruiz-Garcia has presented the paper entitled “Evaluación de la robustez de una red neuronal desarrollada para generar un acelerador HW” written by J.C. Ruiz-García, D. Andrés-Martínez and J. Gracia-Morán at Jornadas SARTECO 2023.

During the Jornadas SARTECO 2023, J. Gracia-Morán has presented the papers entitled “Protección de comunicaciones entre vehículos autónomos mediante el uso de códigos de corrección de errores” written by J. Gracia-Morán, A. Vicente-García and L.J. Saiz-Adalid; and “Uso de códigos de corrección de errores asimétricos en un sistema empotrado” written by J. Gracia-Morán, J.C. Ruiz-García […]

The paper entitled “Hardware Accelerating a Convolutional Neural Network Using High-Level Synthesis”, authored by David de Andrés and Juna Carlos Ruiz has been presented at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

The paper entitled “Comparison of the overheads provoked by the inclusion of different Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás, and P.J. Gil-Vicente has been presented at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

The paper entitled “Hardware Accelerating a Convolutional Neural Network Using High-Level Synthesis”, authored by David de Andrés and Juna Carlos Ruiz has been accepted at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023). Abstract Nowadays, the deployment of deep learning solutions at the edge in industrial, automotive, or medical environments, to cite […]

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