Paper awarded at ITACA Institute

March 6, 2023 | | Comments Off on Paper awarded at ITACA Institute

The paper entitled «A Multi-criteria Analysis of Benchmark Results With Expert Support for Security Tools» written by Miquel Martínez, Juan-Carlos Ruiz, Nuno Antunes, David de Andrés and Marco Vieira, and publised at IEEE Transactions on Dependable and Secure Computing journal has been awarded by the ITACA Institute.

Abstract. The benchmarking of security tools is endeavored to determine which tools are more suitable to detect system vulnerabilities or intrusions. The analysis process is usually oversimplified by employing just a single metric out of the large set of those available. Accordingly, the decision may be biased by not considering relevant information provided by neglected metrics. This paper proposes a novel approach to take into account several metrics, different scenarios, and the advice of multiple experts. The proposal relies on experts quantifying the relative importance of each pair of metrics towards the requirements of a given scenario. Their judgments are aggregated using group decision making techniques, and pondered according to the familiarity of experts with the metrics and scenario, to compute a set of weights accounting for the relative importance of each metric. Then, weight-based multi-criteria-decision-making techniques can be used to rank the benchmarked tools. The usefulness of this approach is showed by analyzing two different sets of vulnerability and intrusion detection tools from the perspective of multiple/single metrics and different scenarios.

9th International Workshop on Safety and Security of Intelligent Vehicles

March 6, 2023 | | Comments Off on 9th International Workshop on Safety and Security of Intelligent Vehicles

David de Andrés is part of the Programm Committee of the 9th International Workshop on Safety and Security of Intelligent Vehicles. This workshop, co-located with DSN 2023, will be celebrated in Porto (Portugal), June 26, 2023.

Fault injection at ISOLDE Project

February 13, 2023 | | Comments Off on Fault injection at ISOLDE Project

Juan Carlos Ruiz and David de Andrés will collaborate in the ISOLDE project (High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems), from the Horizon Europe Framework Programme (HORIZON). They will be responsible of different fault-injection tasks:

– Bit accurate FPGA-fault injection tool with relevant fault-models development.
– Bit accurate FPGA-fault injection tool adaptation to target RISC-V platform.

Paper accepted at DATE 2023

November 21, 2022 | | Comments Off on Paper accepted at DATE 2023

The paper entitled “BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes”, authored by Ilya Tuzov, David de Andres, Juan-Carlos Ruiz and Carles Hernandez has been accepted at DATE 2023.

Abstract

FPGA-based fault injection (FFI) is an indispensable technique for verification and dependability assessment of FPGA designs and prototypes. Existing FFI tools make use of Xilinx essential bits technology to locate the relevant fault targets in FPGA configuration memory (CM). Most FFI tools treat essential bits as black-box, while few of them are able to filter essential bits on the area basis (grid coordinates) in order to selectively target design components contained within the predefined Pblocks. This approach, however, remains insufficiently precise since the granularity of Pblocks in practice does not reach the smallest design (netlist) components. This paper proposes an open-source FFI tool that enables much more fine-grained FFI experiments for Xilinx 7-series and Ultrascale+ FPGAs. By mapping the essential bits with the hierarchical netlist, it allows to precisely target any component in the design tree (up to an individual LUT or register), without the need for defining Pblocks (floorplanning). With minimal experimental effort it estimates the contribution of each DUT component into the resulting dependability features, and discovers weak points of the DUT. Through case studies we show how the proposed tool can be exploited to setup FFI experiments for different kinds of DUTs: from small-footprint microcontrollers, up to multicore RISC-V SoC. The correctness of FFI results is validated by means of RT-level and gate-level simulation-based fault injection.


Keywords: Fault injection, FPGA, configuration memory, robustness assessment, RISC-V

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Keynote speech at EDCC 2022

October 4, 2022 | | Comments Off on Keynote speech at EDCC 2022

Juan Carlos Ruiz-García has given the Keynote Speech entitled “Reconfigurable logic for automotive edge computing: from promises to dependability assessment challenges” inside the Critical Automotive applications: Robustness & Safety (CARS) workshop, at EDCC 2022.

Paper presented at EDCC 2022

October 4, 2022 | | Comments Off on Paper presented at EDCC 2022

David de Andrés has presented the paper entitled “Reversing FPGA architectures for speeding up fault injection: does it pay?” authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz at 18th European Dependable Computing Conference (EDCC 2022).

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Presentation at Jornadas SARTECO 2022 (II)

September 28, 2022 | | Comments Off on Presentation at Jornadas SARTECO 2022 (II)

Joaquín Gracia-Morán has presented the paper “Análisis del impacto de la inclusión de Códigos Correctores de Errores en un Sistema Empotrado basado en Arduino”, authored by Joaquín Gracia-Morán and Luis-J. Saiz-Adalid.

Abstract

El aumento en la escala de integración de los circuitos CMOS ha posibilitado la implementación de sistemas de memoria con una gran capacidad de almacenamiento, pero a costa de aumentar su tasa de fallos. Una posible solución es la inclusión de Códigos de Corrección de Errores (ECCs). Este mecanismo de tolerancia a fallos permite proteger a los sistemas de memoria frente a fallos simples o múltiples.
En un trabajo anterior, estudiamos el impacto que tenía la inclusión de diferentes ECCs en un sistema empotrado. Este tipo de entorno presenta como características básicas un bajo consumo de energía, un peso y volumen reducidos, y una capacidad de cómputo y de memoria no muy alta. Además, su sistema de memoria ya está implementado, con lo que normalmente no se puede añadir hardware para implementar un ECC. En concreto, el sistema empotrado estudiado tenía una arquitectura ARM-Cortex M4 con una SDRAM de 64 Mbit.
A partir de este estudio, surge la duda sobre qué pasaría con un sistema con menos capacidad. Por ejemplo, con un sistema basado en Arduino. En este trabajo respondemos a esta pregunta. Para ello, hemos implementado los mismos ECCs del trabajo anterior, así como otros nuevos con diferentes capacidades de tolerancia a fallos, en un sistema basado en Arduino.

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Presentation at Jornadas SARTECO 2022 (I)

September 28, 2022 | | Comments Off on Presentation at Jornadas SARTECO 2022 (I)

Luis J. Saiz-Adalid has presented the paper “Evaluación de un Microprocesador RISC con capacidad de tolerancia a fallos”, authored by Joaquín Gracia-Morán, Juan C. Baraza, Daniel Gil, Pedro Gil Vicente and Luis-J. Saiz-Adalid.

Abstract

Con la continua reducción de tamaño de la tecnología CMOS, la probabilidad de sufrir tanto fallos simples como múltiples en los sistemas de memoria aumenta. Así pues, son necesarios Mecanismos de Tolerancia a Fallos (MTF) que los protejan. Tradicionalmente, se han utilizado diferentes Códigos Correctores de Errores (ECC) para este fin. A la hora de añadir un ECC a un sistema informático, se debe tener en cuenta las diferentes sobrecargas en el área de silicio, retardo y consumo de energía que introducen los circuitos codificadores y decodificadores, así como la memoria adicional necesaria para almacenar los bits redundantes utilizados por el ECC.
En este trabajo hemos estudiado el comportamiento y las sobrecargas introducidas al añadir diferentes ECC en un modelo en VHDL de un microprocesador RISC. Estos ECC
corrigen errores implementando diversas estrategias de tolerancia a fallos. De esta forma, hemos comparado diversos parámetros, como son el área, el consumo de energía y la tolerancia a fallos de los diferentes modelos implementados de microprocesador RISC tolerante a fallos.

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Session chair at Jornadas SARTECO 2022

September 28, 2022 | | Comments Off on Session chair at Jornadas SARTECO 2022

Last wednesday (September 21st), Joaquín Gracia-Moran has chaired the Fault Tolerant Session at Jornadas SARTECO.

Papers included were:

“Estudio académico de la Fiabilidad de diferentes propuestas de Tolerancia a Fallos para el desarrollo de prácticas docentes”, Rafael Ayllón Gavilán, José Manuel Palomares Muñoz and Joaquín Olivares
“Simulador Web de Sistemas Tolerantes a Fallos”, Antonio Gómez López, Iago Rafael Martínez Sánchez, José Manuel Palomares Muñoz, Joaquín Olivares Bueno and Fernando León García
“Redundancia multihilo para la mitigación de Soft errors en Sistemas on Chip multinúcleo”, Alejandro Serrano Cases, Antonio Martínez-Álvarez, Rodrigo Possamai Bastos and Sergio Cuenca Asensi
“Evaluación de los efectos de los neutrones térmicos a diferentes ángulos de incidencia en una FPGA COTS de 28-nm”, Juan Carlos Fabero, Golnaz Korkian, Francisco Javier Franco, Hortensia Mecha and Juan Antonio Clemente

Keynote speech at EDCC 2022

September 5, 2022 | | Comments Off on Keynote speech at EDCC 2022

Juan Carlos Ruiz-García has been invited by the EDCC 2022 Steering Committe to give a Keynote Speech entitled “Reconfigurable logic for automotive edge computing: from promises to dependability assessment challenges”, inside the Critical Automotive applications: Robustness & Safety (CARS) workshop.

Abstract:

Reconfigurable logic devices have provided means to meet the requirements of evolution existing in parts of modern automotive embedded HW systems. The combination of hard (fast) and reconfigurable (flexible) logic, leads the promise of automotive-graded HW platforms enabling manufacturers to tailor accelerators to specific applications and models. In such a way, HW platforms can be customized attending to the needs of each embedded subsystem to provide higher levels of performance at lower levels of power consumption, and (re-)adjust parts of the logic attending to the set of safety requirements under consideration, existing threats, and their evolution along the time. Despite the high potential of this technology to produce more sophisticated automotive systems, its practical exploitation poses serious doubts in part due to the many challenges that must be addressed when assessing the robustness of the hardware running in the system reconfigurable logic. Although the ISO 26262 standard recommends the use of experimental fault injection for this type of assessment, the spatial and temporal complexity of the logic implementation and the various fault models to consider leads to very long injection campaigns that are unaffordable in practice. One solution is to decrease the level of detail of implementations and inject faults on high-level logic models. Another possibility consists in reducing the number of faults to inject to decrease the experimental time.  Both solutions are largely used in the domain, but one must be aware about the existing implications on accuracy and representativity of results. This keynote speech explores this problem, identifying the challenges existing when dealing with experimental fault injection on reconfigurable logic and proposing some solutions to make this type of dependability assessment feasible.