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Different papers authored by the GSTF’s members has been accepted at Jornadas SARTECO 2025, that will be held in Sevilla (Spain) next June.

Title: Análisis de la confiabilidad de una red neuronal implementada en Arduino con formato BF16
Authors: Joaquín Gracia-Morán, David de Andrés, Luis-J. Saiz-Adalid, Juan Carlos Ruiz, J.-Carlos Baraza-Calvo, Daniel Gil-Tomás, Pedro J. Gil-Vicente
Abstract: El uso de redes neuronales se ha expandido a entornos tan diversos como dispositivos industriales, sistemas médicos o sistemas espaciales. En estos casos, es fundamental equilibrar rendimiento, consumo energético y área de silicio. Además, en entornos críticos, es necesario garantizar una alta
tolerancia a fallos.
Tradicionalmente, las redes neuronales han utilizado parámetros en coma flotante de 32 bits, lo que implica un alto consumo de memoria y una mayor vulnerabilidad a fallos debido a la miniaturización de la tecnología CMOS. Una estrategia efectiva para optimizar estos sistemas es reducir la precisión de los parámetros, utilizando menos bits y disminuyendo así la cantidad de memoria necesaria y el tiempo de procesamiento.
Sin embargo, surgen dudas al implementar este tipo de redes en sistemas empotrados: ¿Mantienen su confiabilidad en entornos críticos, o requieren mecanismos de tolerancia a fallos? ¿Realmente se reduce el área y la latencia?
Este trabajo aborda estas cuestiones reduciendo la precisión de una red neuronal, e implementándola en un sistema basado en Arduino. Además, se han incorporado Códigos de Corrección de Errores y, mediante la técnica de inyección de fallos, se ha evaluado su confiabilidad comparándola con la misma red, pero con sus parámetros codificados en 32 bits.

Title: Implementación en Arduino de una red neuronal cuantizada tolerante a fallos
Authors: Joaquín Gracia-Morán, David de Andrés, Luis-J. Saiz-Adalid, Juan Carlos Ruiz, J.-Carlos Baraza-Calvo, Daniel Gil-Tomás, Pedro J. Gil-Vicente
Abstract: En la actualidad, las redes neuronales se están utilizando en dominios tan dispares como son los entornos industriales, espaciales y médicos, entornos donde es esencial equilibrar rendimiento, consumo energético y área de silicio. Si, además, estos dispositivos forman parte de un sistema crítico, también se debe garantizar una alta tolerancia a fallos.
Generalmente, los parámetros de las redes neuronales se definen en coma flotante de 32 bits, lo que implica un elevado consumo de memoria. Debido a la miniaturización de la tecnología CMOS, la memoria es más susceptible a los fallos múltiples, lo que puede afectar negativamente a los parámetros de la red neuronal almacenados en memoria.
Para optimizar el uso de memoria y acelerar el procesamiento, una estrategia efectiva es reducir la precisión de los parámetros, codificándolos con menos bits. Sin embargo, al implementar estas redes optimizadas en sistemas empotrados, surgen varios interrogantes: ¿realmente se reduce el área ocupada y la latencia? ¿Siguen siendo confiables en entornos críticos?
Este estudio aborda estas cuestiones. Para ello, se han cuantizado a enteros de 8 bits los parámetros de una red neuronal y se ha implementado en un sistema Arduino, incorporando Códigos de Corrección de Errores. A través de la inyección de fallos, se ha analizado su confiabilidad y comparado con una red con los parámetros en coma flotante de 32 bits. Los resultados ayudarán a evaluar si esta optimización mejora el rendimiento sin comprometer la robustez en aplicaciones críticas.

Title: Hacia la evaluación en software de la robustez de aceleradores hardware para CNN cuantizadas
Authors: Juan Carlos Ruiz, David de Andrés, Juan Carlos Baraza, Luis José Saiz-Adalid, Joaquín Gracia-Morán
Abstract: Gracias a su bajo consumo de memoria y energía, así como a su mayor velocidad de ejecución, las redes neuronales convolucionales cuantizadas son especialmente adecuadas para sistemas empotrados que realizan análisis de imágenes. Estos beneficios aumentan al implementarse sobre aceleradores hardware, generados a partir de modelos software mediante herramientas de síntesis de alto nivel y automatización de diseño electrónico. En sistemas críticos, donde se requieren garantías de seguridad funcional, resulta imprescindible evaluar la robustez de estos aceleradores frente a fallos accidentales y maliciosos que pueden alterar su comportamiento nominal durante su ciclo de vida. Realizar dicha evaluación en fases tempranas del desarrollo de la red reduce costes, pero los modelos software disponibles en dichas etapas rara vez reflejan con precisión el comportamiento del hardware. Este trabajo propone una metodología de inyección de fallos, diseñada para modelos software de redes neuronales convolucionales cuantizadas, que busca reproducir fielmente los efectos que los bit-flips pueden tener en el proceso de inferencia de la red una vez que ´esta es implementada sobre un acelerador hardware. La metodología se valida con una versión cuantizada de LeNet descrita en Python. Esta contribución sienta las bases para una evaluación temprana y representativa de la robustez de redes convolucionales cuantizadas, con el objetivo de facilitar el diseño de soluciones futuras de inteligencia artificial embebida más seguras y confiables.

The ITACA Institute has echoed the attendance of GSTF researchers at EDCC 2025. The complete information can be seen here.

The poster entitled “Towards a novel 8-bit floating point format to increase robustness in CNNs”, written by Luis J. Saiz-Adalid, has been awarded as Distinguished Poster at EDCC 2025.

Congratulations!!

The paper entitled “A Hybrid Technique based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM arrays“, written by Daniel Gil-Tomás, Luis J. Saiz-Adalid, Joaquín Gracia-Morán, J. Carlos Baraza-Calvo and Pedro J. Gil-Vicente has been awarded by the third prize for the publication with the highest impact factor 2024 from the ITACA Institute.

Abstract:

MBU is an increasing challenge in SRAM memory, due to the chip’s large area of SRAM, and supply power scaling applied to reduce static consumption. Powerful ECCs can cope with random MBUs, but at the expense of complex encoding/decoding circuits, and high memory redundancy. Alternatively, radiation-hardened cell is an alternative technique that can mask single or even double node upsets in the same cell, but at the cost of increasing the overhead of the memory array. The idea of this work is to combine both techniques to take advantage of their respective strengths. To reduce redundancy and encoder/decoder overheads, SEC Hamming ECC has been chosen. About hardened cells, well-known and robust DICE cells, able to tolerate one node upset, have been used. To assess the proposed technique, we have measured the correction capability after a fault injection campaign, as well as the overhead (redundancy, area, power, and delay) of memory and encoding/decoding circuits. Results show high MBU correction coverages with an affordable overhead. For instance, for very harmful 8-bit random MBUs injected in the same memory word, more than 80% of the cases are corrected. Area overhead values of our proposal, measured with respect to double and triple error correction codes, are less than x1.45. To achieve the same correction coverage only with ECCs, redundancy, and overhead would be much higher.

Several members of the group have traveled to Lisbon to participate in EDCC 2025, where they have presented the future work we are doing.

Our colleague David de Andrés has been appointed as administration manager of the ITACA Institute at Universitat Politècnica de València.

Congratulations!

During next EDCC (20th European Dependable Computing Conference), that will be held in Lisbon (Portugal) in April 2025, the GSTF research group will present three extended fast-abstracts, showing our current research lines.
These works are:

Title: Towards a Novel 8-bit Floating-point Format to Increase Robustness in Convolutional Neural Networks

Authors: Luis-J. Saiz Adalid, Juan-Carlos Ruiz-García, Joaquín Gracia-Morán, David de Andrés, J.-Carlos Baraza-Calvo, Daniel Gil-Tomás, Pedro Gil-Vicente

Abstract: Convolutional Neural Networks (CNNs) are widely adopted in Artificial Intelligence applications, particularly in computer vision and other deep learning tasks. Their performance relies on millions of parameters, including weights and biases, which are optimized during training, stored, and utilized during inference. Traditionally, these parameters are represented using the 32-bit IEEE-754 single-precision floating-point format. However, research has shown that excess precision in this format is not always required to maintain accuracy, motivating the adoption of reduced-precision 16-bit formats. A natural progression of this trend is representing real numbers using 8-bit formats. However, existing proposals often suffer from precision loss, negatively impacting CNN accuracy. In this extended abstract, we propose a novel 8-bit floating-point format designed to enhance reliability in CNNs, due to its reduced memory footprint, enough precision, and well-fitted range. We evaluate its advantages and limitations through comparative analysis. Initial findings suggest that our format improves computational efficiency while preserving accuracy comparable to 32-bit networks, increasing reliability. However, further experimental validation is necessary.

Title: Towards SW-based Robustness Assessment of HW Accelerators for Quantized CNNs

Authors: Juan Carlos Ruiz, David de Andrés, Juan-Carlos Baraza-Calvo, Luis-José Saiz-Adalid,
Joaquín Gracia-Morán, Daniel Gil-Tomás, Pedro Gil-Vicente

Abstract: Quantized Convolutional Neural Networks (QCNNs) are widely adopted in resource-limited environments due to their reduced memory footprint, lower power consumption, and faster execution. Hardware (HW) accelerators further enhance these benefits by optimizing QCNN execution for available resources, a crucial aspect in embedded systems. Typically, the development cycle of neural networks begins with a software (SW) model, which is later refined and implemented in HW. Leveraging this initial SW model for early robustness assessments is an attractive approach, as it allows fault tolerance evaluation before committing to HW implementation. However, for such assessments to be meaningful, they must accurately reflect the fault behavior that would occur in HW. This paper examines the limitations of naive fault injection approaches in SW-based QCNN models and demonstrates how they can lead to misleading conclusions about HW robustness. The key issue arises from the internal multi-component representation of quantized parameters, which differs from direct floating-point storage. Our analysis highlights that simplistic bit-flip injections in SW-based QCNNs do not necessarily translate to equivalent faults in their HW implementations, leading to inaccuracies in robustness evaluation. While we do not propose a specific fault injection methodology, we identify critical challenges that must be addressed to ensure that early-stage SW evaluations on QCNNs have potential to provide valid, cost-effective insights into the resilience of their HW implementations.

Title: Initial insights into synthesis overheads caused by C-based Error Correction Codes implementations

Authors: Joaquín Gracia-Morán, David de Andrés, Luis-J. Saiz-Adalid, Juan Carlos Ruiz, J.-Carlos Baraza-Calvo, Daniel Gil-Tomás, Pedro J. Gil-Vicente

Abstract: Error Correction Codes (ECCs) are increasingly used in safety-critical systems, such as hardware accelerators for cryptographic computations and neural network inference. These systems require high reliability, making ECCs essential for mitigating soft errors and improving fault tolerance. Thus, the demand for efficient ECC implementations is rising, necessitating faster design and deployment processes. Traditional hardware design approaches, such as Register-Transfer Level (RTL) development, can be time-consuming and very complex. High-Level Synthesis (HLS) enables the automatic transformation of C-based ECC models into hardware descriptions, reducing development effort while allowing design-space exploration. This methodology facilitates rapid prototyping and optimization, enabling the evaluation of different architectural choices without manually modifying the RTL code. However, coding styles, algorithmic transformations, and optimization strategies in C-based can directly affect the synthesized hardware’s performance metrics, including area utilization, power consumption, and latency.
This work provides initial insights into how different C-based ECC design choices influence the final hardware implementation. To do this, we have analyzed synthesis results under various ECC configurations.

The paper entitled “Allocating ECC parity bits into BF16-encoded CNN parameters: A practical experience report” written by Joaquín Gracia-Morán, Juan Carlos Ruiz Garcia, David de Andrés Martínez and Luis Jose Saiz-Adalid is available at ACM: https://dl.acm.org/doi/10.1145/3697090.3697092

Abstract

Using low-precision data types, like the Brain Floating Point 16 (BF16) format, can reduce Convolutional Neural Networks (CNNs) memory usage in edge devices without significantly affecting their accuracy. Adding in-parameter zero-space Error Correction Codes (ECCs) can enhance the robustness of BF16-based CNNs. However, implementing this technique raises practical questions. For instance, when the available invariant1 and non-significant2 bits in parameters for error correction are sufficient for the required protection level, the proper selection and combination of these bits become crucial. On the other hand, if the set of available bits is inadequate, converting nearly invariant bits to invariants might be considered. These decisions impact ECC decoder complexity and may affect the overall CNN performance. This report examines such implications using Lenet-5 and GoogLenet as case studies.

The paper entitled “Allocating ECC parity bits into BF16-encoded CNN parameters: A practical experience report” written by Joaquín Gracia-Morán, Juan Carlos Ruiz Garcia, David de Andrés Martínez and Luis Jose Saiz-Adalid has been accepted at 13th Latin-American Symposium on Dependable and Secure Computing (LADC 2024), that will be held in Recife (Brazil) next November.

Abstract

Using low-precision data types, like the Brain Floating Point 16 (BF16) format, can reduce Convolutional Neural Networks (CNNs) memory usage in edge devices without significantly affecting their accuracy. Adding in-parameter zero-space Error Correction Codes (ECCs) can enhance the robustness of BF16-based CNNs. However, implementing this technique raises practical questions. For instance, when the available invariant1 and non-significant2 bits in parameters for error correction are sufficient for the required protection level, the proper selection and combination of these bits become crucial. On the other hand, if the set of available bits is inadequate, converting nearly invariant bits to invariants might be considered. These decisions impact ECC decoder complexity and may affect the overall CNN performance. This report examines such implications using Lenet-5 and GoogLenet as case studies.

The paper entitled “In-Memory Zero-Space Floating-Point-based CNN protection using non-significant and invariant bits”, and written by Juan Carlos Ruiz Garcia, Luis Jose Saiz-Adalid, David de Andrés Martínez, and Joaquín Gracia-Morán, published at SAFECOMP 2024, can be accesed at this link.

Abstract

Convolutional Neural Networks (CNNs) have accomplished significant success in various domains, including transportation, health care and banking. Millions of weights, loaded from main memory into the internal buffers of CNN accelerators, are repeatedly used in the inference process. Accidental and malicious bit-flips targeting these buffers may negatively impact the CNN’s accuracy. This paper proposes a methodology to tolerate the effect of (multiple) bit-flips on floating-point-based CNNs using the non-significant and the invariant bits of CNN parameters. The former, determined after fault injection, do not significantly affect the accuracy of the inference process regardless of their value. The latter, determined after analyzing the network parameters, have the same value for all of them. Slight modifications can be applied to carefully selected parameters to increase the number of invariant bits. Since non-significant and invariant bits do not require protection against faults, they are employed to store the parity bits of error control codes. The methodology preserves the CNN accuracy, keeps its memory footprint, and does not require any retraining. Its usefulness is exemplished through the FP32 and BFloat16 versions of the LeNet-5 and GoogleNet CNNs.

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