Paper accepted at EDCC 2024

January 31, 2024 | | Comments Off on Paper accepted at EDCC 2024

The paper entitled “Zero-Space In-Weight and In-Bias Protection for Floating-Point-based CNNs”, written by Juan Carlos Ruiz, David de Andrés, Luis José Saiz-Adalid and Joaquín Gracia-Morán has been accepted at 19th European Dependable Computing Conference (EDCC), that will be held in Leuven (Belgium) next april.

Abstract

Deploying convolutional neural networks (CNNs) in image classification systems requires balancing conflicting goals, like throughput, power consumption, and silicon area. In safety-critical environments, ensuring acceptable levels of robustness against faults is also of utmost importance. The robustness gains promoted by quantised CNNs entail a loss of accuracy that may be problematic for some applications. Traditional redundancy-based solutions provide high error coverage at the cost of high, and sometimes unaffordable, overheads, especially for resource constrained solutions. This paper proposes using error correction codes (ECC) to protect the tensors of CNNs from potential inadvertent corruption. Fault injection is used to locate all bits in tensors that, even if corrupted, do not affect the network inference process. These bits are then replaced by computed parity bits. By exploiting the intrinsic robustness of CNNs, no additional memory bits are required to store the parity bits while preserving both the ECC protection guarantees and the CNN inference accuracy. The proposal applies conventional, conservative, and aggressive policies depending on the required degree of protection and the overhead the system can afford. The usefulness of these alternatives is exemplified through a floating-point-based CNN that is prototyped on a programmable logic device. Unlike existing solutions, the approach can be deployed without retraining, using well-known and proven ECCs and at an in-memory zero-space cost.

Presentation at Jornadas SARTECO 2023 (II)

September 25, 2023 | | Comments Off on Presentation at Jornadas SARTECO 2023 (II)

J.C. Ruiz-Garcia has presented the paper entitled “Evaluación de la robustez de una red neuronal desarrollada para generar un acelerador HW” written by J.C. Ruiz-García, D. Andrés-Martínez and J. Gracia-Morán at Jornadas SARTECO 2023.

Presentation at Jornadas SARTECO 2023 (I)

September 25, 2023 | | Comments Off on Presentation at Jornadas SARTECO 2023 (I)

During the Jornadas SARTECO 2023, J. Gracia-Morán has presented the papers entitled “Protección de comunicaciones entre vehículos autónomos mediante el uso de códigos de corrección de errores” written by J. Gracia-Morán, A. Vicente-García and L.J. Saiz-Adalid; and “Uso de códigos de corrección de errores asimétricos en un sistema empotrado” written by J. Gracia-Morán, J.C. Ruiz-García and L.J. Saiz-Adalid.

Welcome Day at Master’s Degree in Computer and Network Engineering

September 19, 2023 | | Comments Off on Welcome Day at Master’s Degree in Computer and Network Engineering

Juan Carlos Ruiz, academic director of the Master’s Degree in Computer and Network Engineering, has welcomed the new students of our master.

Paper presented at ITACA-WIICT 2023 (II)

July 10, 2023 | | Comments Off on Paper presented at ITACA-WIICT 2023 (II)

The paper entitled “Hardware Accelerating a Convolutional Neural Network Using High-Level Synthesis”, authored by David de Andrés and Juna Carlos Ruiz has been presented at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023).

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Paper presented at ITACA-WIICT 2023 (I)

July 10, 2023 | | Comments Off on Paper presented at ITACA-WIICT 2023 (I)

The paper entitled “Comparison of the overheads provoked by the inclusion of different Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás, and P.J. Gil-Vicente has been presented at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023).

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Paper accepted at ITACA-WIICT 2023 (II)

June 29, 2023 | | Comments Off on Paper accepted at ITACA-WIICT 2023 (II)

The paper entitled “Hardware Accelerating a Convolutional Neural Network Using High-Level Synthesis”, authored by David de Andrés and Juna Carlos Ruiz has been accepted at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023).

Abstract

Nowadays, the deployment of deep learning solutions at the edge in industrial, automotive, or medical environments, to cite a few, requires balancing different conflicting goals, like throughput, power consumption, silicon area, and robustness. Hence, the high throughput per watt of programmable-logic devices makes them suitable candidates to act as hardware accelerators for convolutional neural networks. However, it is a daunting task to model such networks at the register-transfer level, using a hardware description language, to implement them on the target technology efficiently. In recent years, high-level synthesis has provided an additional abstraction level, so hardware designers can focus on describing the behaviour of a system, and automated tools generate the detailed micro-architecture. This approach can reduce the cost of developing custom hardware accelerators for neural networks. Still, several parameters, compilation directives, and code transformations should be adequately applied to optimise the resulting implementation. This practical experience report presents a case study of a C description of a LeNet-5 convolutional neural network architecture and its adaptation to generate an optimised hardware implementation using high-level synthesis.

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Paper accepted at ITACA-WIICT 2023 (I)

June 29, 2023 | | Comments Off on Paper accepted at ITACA-WIICT 2023 (I)

The paper entitled “Comparison of the overheads provoked by the inclusion of different Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás, and P.J. Gil-Vicente has been accepted at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023).

Abstract

During these last years, the use of embedded systems has grown exponentially, mainly due to the expansion of the Internet of Things (IoT). Data collected by IoT devices are sent to the cloud to be processed in datacenters. Edge Computing philosophy wants to change this “passive” behavior of IoT devices. The basic idea is to process data produced by IoT devices closer to where they were created, instead of sending them through long routes.

New challenges have emerged with the change to the Edge Computing philosophy. One of them is reliability. IoT devices have been built with low-reliable components, reduced weight and volume, and not very high computing and memory capacity for low power consumption. With these conditions, how can we rely on the results obtained by these devices? In this work, we have tried to answer this question by analyzing the effects of the inclusion of different software-implemented Error Correction Codes in real embedded systems, typically used in IoT.

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Paper accepted at Jornadas SARTECO 2023 (III)

June 29, 2023 | | Comments Off on Paper accepted at Jornadas SARTECO 2023 (III)

The paper entitled “Evaluación de la robustez de una red neuronal desarrollada para generar un acelerador HW” written by J.C. Ruiz-García, D. Andrés-Martínez and J. Gracia-Morán has been accepted at Jornadas SARTECO 2023.

Abstract

El uso combinado de lenguajes de programación de alto nivel con herramientas de automatización de diseño electrónico , facilita el desarrollo de modelos de redes neuronales sintetizables sobre lógica programable. Aunque específicos, los aceleradores HW así producidos pueden optimizarse para ofrecer un buen balance entre prestaciones, área de silicio ocupada y consumo. Esto los hace especialmente interesantes en ámbitos donde los recursos disponibles son limitados, como en el IoT o la automoción. Sin embargo, su interés final puede variar en cada contexto atendiendo a los requisitos que se impongan en materia de seguridad funcional y que fijarán el grado de robustez esperado del modelo. Este artículo propone una metodología de evaluación, mediante inyección de fallos,que permite determinar la robustez de una red neuronal frente a alteraciones accidentales de sus pesos y sesgos. El modelo considerado es el de una red neuronal convolucional de tipo Lenet-5 implementada en C que posee un error de predicción del 1.83 %. Los resultados muestran que, en ocasiones, la modificación de un único bit en uno de los pesos/sesgos considerados puede llevar a la red a realizar predicciones incorrectas. No obstante, se constata que, en líneas generales,su naturaleza estocástica permite a la red tolerar el efecto de la mayor parte de los fallos inyectados, con un impacto mínimo, aunque no despreciable, en su precisión, y por tanto, en su seguridad funcional.

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Paper accepted at Jornadas SARTECO 2023 (II)

June 29, 2023 | | Comments Off on Paper accepted at Jornadas SARTECO 2023 (II)

The paper entitled “Protección de comunicaciones entre vehículos autónomos mediante el uso de códigos de corrección de errores” written by J. Gracia-Morán, A. Vicente-García and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2023.

Abstract

La reducción de tamaño de la tecnología CMOS ha permitido aumentar las prestaciones de los sistemas empotrados. Sin embargo, esta disminución de tamaño implica un aumento en la tasa de fallos. En este sentido, cobra gran importancia la protección, de forma sencilla y rápida, de los datos que procesan estos sistemas.

Uno de los aspectos más importantes de los sistemas empotrados es su consumo de energía. Por ejemplo, a la hora de transmitir un dato, si este se recibe de forma errónea, hay que pedir su retransmisión, lo que conlleva un gasto de energía no previsto. Es por ello por lo que parece interesante proteger los datos a intercambiar.

Si bien los códigos de corrección de errores (ECC) se han utilizado tradicionalmente para proteger sistemas de memoria o para transmisiones masivas de datos, también se pueden utilizar para proteger datos de pocos bits transmitidos por una red de comunicaciones. En este trabajo, utilizando dos prototipos de vehículos autónomos no tripulados basados en Arduino que se comunican entre sí, y mediante diferentes ECC, hemos estudiado la confiabilidad de la comunicación entre ellos. Con el estudio de diferentes ECC se pretende valorar y analizar la mejora obtenida en la confiabilidad, así como el sobrecoste en el que se incurre, cuestión importante en sistemas empotrados.

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033