Programm Committee Members of the VIII Jornadas de Computación Empotrada y Reconfigurable (JCER’24)

March 22, 2024 | | Comments Off on Programm Committee Members of the VIII Jornadas de Computación Empotrada y Reconfigurable (JCER’24)

Joaquín Gracia-Morán and Juan C. Ruiz-García will serve as members of the Programm Committee of the VIII Jornadas de Computación Empotrada y Reconfigurable (JCER’24), that will be held in A Coruña next June.

Paper accepted at IEEE Latin American Transactions

March 7, 2024 | | Comments Off on Paper accepted at IEEE Latin American Transactions

The paper entitled “A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words”, written by J. Gracia-Morán (ORCID), L. J. Saiz-Adalid (ORCID), J. C. Baraza-Calvo (ORCID), D. Gil-Tomás (ORCID) and P. J. Gil-Vicente (ORCID), has been accepted at IEEE Latin American Transactions.

Video Summary here

Abstract

Actual memory systems provide large storage capacity thanks to the integration scale level achieved in CMOS technology. This increment in storage capacity comes with an augment on their fault rate. In this way, the probability of experiencing Single or Multiple Cell Upsets has risen. Error Correction Codes (ECC) are a fault-tolerant mechanism broadly employed to protect memory systems. Usually, an ECC-based fault tolerance mechanism is designed with fixed correction and detection capabilities. However, in some contexts, current memory systems can suffer a variable fault rate during their operation. Thus, it seems very interesting that this fault-tolerant mechanism would be able to adapt to these variable fault conditions.
This work proposes an Adaptive Fault-Tolerant mechanism based on ECC. This mechanism can adapt to different fault conditions, being able to correct and/or detect single and multiple bits in error. The Adaptive Fault-Tolerant mechanism proposed uses a unique encoder and various decoders. Therefore, there is no need to re-encode the data to change the error coverage since the unique encoder and the equal redundancy are the same regardless of the fault tolerance required. In addition, we have studied the area, delay, and power consumption overheads produced by the inclusion of the redundant bits, the encoder, and the decoders of the ECC in a computer system.

Paper accepted at EDCC 2024

January 31, 2024 | | Comments Off on Paper accepted at EDCC 2024

The paper entitled “Zero-Space In-Weight and In-Bias Protection for Floating-Point-based CNNs”, written by Juan Carlos Ruiz, David de Andrés, Luis José Saiz-Adalid and Joaquín Gracia-Morán has been accepted at 19th European Dependable Computing Conference (EDCC), that will be held in Leuven (Belgium) next april.

Abstract

Deploying convolutional neural networks (CNNs) in image classification systems requires balancing conflicting goals, like throughput, power consumption, and silicon area. In safety-critical environments, ensuring acceptable levels of robustness against faults is also of utmost importance. The robustness gains promoted by quantised CNNs entail a loss of accuracy that may be problematic for some applications. Traditional redundancy-based solutions provide high error coverage at the cost of high, and sometimes unaffordable, overheads, especially for resource constrained solutions. This paper proposes using error correction codes (ECC) to protect the tensors of CNNs from potential inadvertent corruption. Fault injection is used to locate all bits in tensors that, even if corrupted, do not affect the network inference process. These bits are then replaced by computed parity bits. By exploiting the intrinsic robustness of CNNs, no additional memory bits are required to store the parity bits while preserving both the ECC protection guarantees and the CNN inference accuracy. The proposal applies conventional, conservative, and aggressive policies depending on the required degree of protection and the overhead the system can afford. The usefulness of these alternatives is exemplified through a floating-point-based CNN that is prototyped on a programmable logic device. Unlike existing solutions, the approach can be deployed without retraining, using well-known and proven ECCs and at an in-memory zero-space cost.

Presentation at Jornadas SARTECO 2023 (II)

September 25, 2023 | | Comments Off on Presentation at Jornadas SARTECO 2023 (II)

J.C. Ruiz-Garcia has presented the paper entitled “Evaluación de la robustez de una red neuronal desarrollada para generar un acelerador HW” written by J.C. Ruiz-García, D. Andrés-Martínez and J. Gracia-Morán at Jornadas SARTECO 2023.

Presentation at Jornadas SARTECO 2023 (I)

September 25, 2023 | | Comments Off on Presentation at Jornadas SARTECO 2023 (I)

During the Jornadas SARTECO 2023, J. Gracia-Morán has presented the papers entitled “Protección de comunicaciones entre vehículos autónomos mediante el uso de códigos de corrección de errores” written by J. Gracia-Morán, A. Vicente-García and L.J. Saiz-Adalid; and “Uso de códigos de corrección de errores asimétricos en un sistema empotrado” written by J. Gracia-Morán, J.C. Ruiz-García and L.J. Saiz-Adalid.

Welcome Day at Master’s Degree in Computer and Network Engineering

September 19, 2023 | | Comments Off on Welcome Day at Master’s Degree in Computer and Network Engineering

Juan Carlos Ruiz, academic director of the Master’s Degree in Computer and Network Engineering, has welcomed the new students of our master.

Paper presented at ITACA-WIICT 2023 (II)

July 10, 2023 | | Comments Off on Paper presented at ITACA-WIICT 2023 (II)

The paper entitled “Hardware Accelerating a Convolutional Neural Network Using High-Level Synthesis”, authored by David de Andrés and Juna Carlos Ruiz has been presented at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023).

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Paper presented at ITACA-WIICT 2023 (I)

July 10, 2023 | | Comments Off on Paper presented at ITACA-WIICT 2023 (I)

The paper entitled “Comparison of the overheads provoked by the inclusion of different Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás, and P.J. Gil-Vicente has been presented at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023).

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Paper accepted at ITACA-WIICT 2023 (II)

June 29, 2023 | | Comments Off on Paper accepted at ITACA-WIICT 2023 (II)

The paper entitled “Hardware Accelerating a Convolutional Neural Network Using High-Level Synthesis”, authored by David de Andrés and Juna Carlos Ruiz has been accepted at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023).

Abstract

Nowadays, the deployment of deep learning solutions at the edge in industrial, automotive, or medical environments, to cite a few, requires balancing different conflicting goals, like throughput, power consumption, silicon area, and robustness. Hence, the high throughput per watt of programmable-logic devices makes them suitable candidates to act as hardware accelerators for convolutional neural networks. However, it is a daunting task to model such networks at the register-transfer level, using a hardware description language, to implement them on the target technology efficiently. In recent years, high-level synthesis has provided an additional abstraction level, so hardware designers can focus on describing the behaviour of a system, and automated tools generate the detailed micro-architecture. This approach can reduce the cost of developing custom hardware accelerators for neural networks. Still, several parameters, compilation directives, and code transformations should be adequately applied to optimise the resulting implementation. This practical experience report presents a case study of a C description of a LeNet-5 convolutional neural network architecture and its adaptation to generate an optimised hardware implementation using high-level synthesis.

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033

Paper accepted at ITACA-WIICT 2023 (I)

June 29, 2023 | | Comments Off on Paper accepted at ITACA-WIICT 2023 (I)

The paper entitled “Comparison of the overheads provoked by the inclusion of different Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás, and P.J. Gil-Vicente has been accepted at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023).

Abstract

During these last years, the use of embedded systems has grown exponentially, mainly due to the expansion of the Internet of Things (IoT). Data collected by IoT devices are sent to the cloud to be processed in datacenters. Edge Computing philosophy wants to change this “passive” behavior of IoT devices. The basic idea is to process data produced by IoT devices closer to where they were created, instead of sending them through long routes.

New challenges have emerged with the change to the Edge Computing philosophy. One of them is reliability. IoT devices have been built with low-reliable components, reduced weight and volume, and not very high computing and memory capacity for low power consumption. With these conditions, how can we rely on the results obtained by these devices? In this work, we have tried to answer this question by analyzing the effects of the inclusion of different software-implemented Error Correction Codes in real embedded systems, typically used in IoT.

DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033