Jun
27
Paper accepted at Jornadas SARTECO 2022 (I)
June 27, 2022 | Comments Off on Paper accepted at Jornadas SARTECO 2022 (I)
The paper entitled “Análisis del impacto de la inclusión de Códigos Correctores de Errores en un Sistema Empotrado basado en Arduino” written by J. Gracia-Morán and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2022. Abstract El aumento en la escala de integración de los circuitos CMOS ha posibilitado la implementación de sistemas de memoria […]
Jun
13
Paper accepted at EDCC 2022
June 13, 2022 | Comments Off on Paper accepted at EDCC 2022
The paper entitled “Reversing FPGA architectures for speeding up fault injection: does it pay?” authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz has been accepted at 18th European Dependable Computing Conference (EDCC 2022), that will be held in Zaragoza (Spain) from 12 to 15 of September. Abstract Although initially considered for fast system […]
Sep
30
WIICT 2021: Fault Tolerant Systems (SCT)
September 30, 2021 | Comments Off on WIICT 2021: Fault Tolerant Systems (SCT)
You can see the video-presentation of our research lines at https://youtu.be/2xtaBYqOVxE Hope you like it!!
Sep
17
Jornadas SARTECO 20/21
September 17, 2021 | Comments Off on Jornadas SARTECO 20/21
Next week, J. Gracia-Moran will present the paper called “Estudio del impacto de la inclusión de Códigos Correctores de Errores en un Sistema Empotrado” in Malaga (Spain), at Jornadas SARTECO 20/21. Abstract En la actualidad, la escala de integración de la tecnología CMOS ha permitido diseñar sistemas de memoria con una gran capacidad de almacenamiento. […]