Jul
15
Paper presented at ITACA-WIICT 2022 (II)
July 15, 2022 | Comments Off on Paper presented at ITACA-WIICT 2022 (II)
The paper entitled “Analysis of overheads caused by adding Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, P.Martín-Tabares, C. Martínez-Ruiz and L.J. Saiz-Adalid has been presented at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Jul
15
Paper presented at ITACA-WIICT 2022 (I)
July 15, 2022 | Comments Off on Paper presented at ITACA-WIICT 2022 (I)
The paper entitled “Tolerating Double and Triple Random Errors with Low Redundancy Error Correction Codes”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás and P.J. Gil-Vicente has been presented at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Jun
29
Paper accepted at ITACA-WIICT 2022 (II)
June 29, 2022 | Comments Off on Paper accepted at ITACA-WIICT 2022 (II)
The paper entitled “Analysis of overheads caused by adding Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, P.Martín-Tabares, C. Martínez-Ruiz and L.J. Saiz-Adalid has been accepted at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). Abstract Nowadays, CMOS technology integration scale has allowed memory systems with a large storage capacity. […]
Jun
29
Paper accepted at ITACA-WIICT 2022 (I)
June 29, 2022 | Comments Off on Paper accepted at ITACA-WIICT 2022 (I)
The paper entitled “Tolerating Double and Triple Random Errors with Low Redundancy Error Correction Codes”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás and P.J. Gil-Vicente has been accepted at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). Abstract With the continuous size reduction of CMOS technology, faults suffered by […]
Jun
27
Paper accepted at Jornadas SARTECO 2022 (II)
June 27, 2022 | Comments Off on Paper accepted at Jornadas SARTECO 2022 (II)
The paper entitled “Evaluación de un Microprocesador RISC con capacidad de tolerancia a fallos” written by J. Gracia-Morán, J.C. Baraza-Calvo, D. Gil-Tomás, P.J. Gil-Vicente and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2022. Abstract Con la continua reducción de tamaño de la tecnología CMOS, la probabilidad de sufrir tanto fallos simples como múltiples en […]
Jun
27
Paper accepted at Jornadas SARTECO 2022 (I)
June 27, 2022 | Comments Off on Paper accepted at Jornadas SARTECO 2022 (I)
The paper entitled “Análisis del impacto de la inclusión de Códigos Correctores de Errores en un Sistema Empotrado basado en Arduino” written by J. Gracia-Morán and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2022. Abstract El aumento en la escala de integración de los circuitos CMOS ha posibilitado la implementación de sistemas de memoria […]
Jun
13
Paper accepted at EDCC 2022
June 13, 2022 | Comments Off on Paper accepted at EDCC 2022
The paper entitled “Reversing FPGA architectures for speeding up fault injection: does it pay?” authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz has been accepted at 18th European Dependable Computing Conference (EDCC 2022), that will be held in Zaragoza (Spain) from 12 to 15 of September. Abstract Although initially considered for fast system […]
Sep
17
Jornadas SARTECO 20/21
September 17, 2021 | Comments Off on Jornadas SARTECO 20/21
Next week, J. Gracia-Moran will present the paper called “Estudio del impacto de la inclusión de Códigos Correctores de Errores en un Sistema Empotrado” in Malaga (Spain), at Jornadas SARTECO 20/21. Abstract En la actualidad, la escala de integración de la tecnología CMOS ha permitido diseñar sistemas de memoria con una gran capacidad de almacenamiento. […]