Jun
13
Paper accepted at EDCC 2022
June 13, 2022 | | Comments Off on Paper accepted at EDCC 2022
The paper entitled “Reversing FPGA architectures for speeding up fault injection: does it pay?” authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz has been accepted at 18th European Dependable Computing Conference (EDCC 2022), that will be held in Zaragoza (Spain) from 12 to 15 of September.
Abstract
Although initially considered for fast system prototyping, Field Programmable Gate Arrays (FPGAs) are gaining interest as targets for implementing final products thanks to their inherent reconfiguration capabilities.
As they are susceptible to soft errors in their configuration memory, the dependability of FPGA-based designs must be accurately evaluated to be used in critical systems.
During the last years, research has focused on speeding up fault injection in FPGA-based systems by parallelising experimentation, reducing the injection time, and decreasing the number of experiments.
Going a step further requires delving into the FPGA architecture, i.e. precisely determining which components are implementing the considered design (mapping) and which of them are exercised by the considered workload (profiling).
After that, fault injection campaigns can focus on just those FPGA components actually used in order to identify critical ones, i.e. those leading the target system to fail.
Some manufacturers, like Xilinx, identify those bits in the FPGA configuration memory that may change the implemented design when affected by a soft error. However, their correspondence to particular components of the FPGA fabric and their relationship with the implementation-level model are yet unknown. This paper addresses the question of whether the effort of reversing an FPGA architecture to filter out redundant and unused essential bits pays in terms of experimental time. Since the work of reversing the complete architecture of an FPGA is titanic, as the first step towards this ambitious goal, this paper focuses on those elements in charge of implementing the combinational logic of the design (Look-Up Tables). The experimental results that support this study derive from implementing three soft-core processors on a Zynq SoC FPGA and show the interest of the proposal.
DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
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