Oct
19
New paper at IEEE Latin American Transactions
October 19, 2021 | | Comments Off on New paper at IEEE Latin American Transactions
The paper entitled “Design, Implementation and Evaluation of a Low Redundant Error Correction Code”, written by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás and P.J. Gil-Vicente is availabe here.
Abstract
The continuous incrementin the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, a single particle hit in a storage element (such as memory or registers) can provokea single error in a memory cell (known asSingle Cell Upsets or SCU),as well as simultaneous errors in more than one memory cell (known asMultiple Cell Upsets or MCU). A common method to tolerate this type of errors is the use of Error Correction Codes (ECC). However, the addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to detect and/or correct errors. An ECC can be designed focusing on different parameters: low redundancy, low delay, error coverage, etc.The design of ECC is a very active field, and ECC with different properties are continuously proposed. However, usually, these proposals only present the ECC, not showing what happens when they are included in a microprocessor. The idea of this paper is twofold. First, we present the design of an ECC whose main characteristic is its low number of code bits (low redundancy). This ECC adds 15 redundant bits to a 32-bit data word to form a (47, 32) ECC able to correct single and doble errors, and to detect triple errors. Second, we also study the overheadsthat this ECC introduceswhen added to a RISC microprocessor, comparing itwith some other well-known ECC.
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