Jun
29
Paper accepted at Jornadas SARTECO 2023 (II)
June 29, 2023 | Comments Off on Paper accepted at Jornadas SARTECO 2023 (II)
The paper entitled “Protección de comunicaciones entre vehículos autónomos mediante el uso de códigos de corrección de errores” written by J. Gracia-Morán, A. Vicente-García and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2023. Abstract La reducción de tamaño de la tecnología CMOS ha permitido aumentar las prestaciones de los sistemas empotrados. Sin embargo, esta […]
Jun
23
Paper accepted at Jornadas SARTECO 2023 (I)
June 23, 2023 | Comments Off on Paper accepted at Jornadas SARTECO 2023 (I)
The paper entitled “Uso de códigos de corrección de errores asimétricos en un sistema empotrado” written by J. Gracia-Morán, J.C. Ruiz-García and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2023. Abstract Durante estos últimos años, el desarrollo tecnológico ha propiciado un aumento en las prestaciones de los sistemas digitales, pero a costa de reducir […]
Nov
21
Paper accepted at DATE 2023
November 21, 2022 | Comments Off on Paper accepted at DATE 2023
The paper entitled “BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes”, authored by Ilya Tuzov, David de Andres, Juan-Carlos Ruiz and Carles Hernandez has been accepted at DATE 2023. Abstract FPGA-based fault injection (FFI) is an indispensable technique for verification and dependability assessment of FPGA designs and prototypes. Existing FFI tools […]
Oct
4
Keynote speech at EDCC 2022
October 4, 2022 | Comments Off on Keynote speech at EDCC 2022
Juan Carlos Ruiz-García has given the Keynote Speech entitled “Reconfigurable logic for automotive edge computing: from promises to dependability assessment challenges” inside the Critical Automotive applications: Robustness & Safety (CARS) workshop, at EDCC 2022.
Oct
4
Paper presented at EDCC 2022
October 4, 2022 | Comments Off on Paper presented at EDCC 2022
David de Andrés has presented the paper entitled “Reversing FPGA architectures for speeding up fault injection: does it pay?” authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz at 18th European Dependable Computing Conference (EDCC 2022). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Sep
28
Presentation at Jornadas SARTECO 2022 (II)
September 28, 2022 | Comments Off on Presentation at Jornadas SARTECO 2022 (II)
Joaquín Gracia-Morán has presented the paper “Análisis del impacto de la inclusión de Códigos Correctores de Errores en un Sistema Empotrado basado en Arduino”, authored by Joaquín Gracia-Morán and Luis-J. Saiz-Adalid. Abstract El aumento en la escala de integración de los circuitos CMOS ha posibilitado la implementación de sistemas de memoria con una gran capacidad […]
Sep
28
Presentation at Jornadas SARTECO 2022 (I)
September 28, 2022 | Comments Off on Presentation at Jornadas SARTECO 2022 (I)
Luis J. Saiz-Adalid has presented the paper “Evaluación de un Microprocesador RISC con capacidad de tolerancia a fallos”, authored by Joaquín Gracia-Morán, Juan C. Baraza, Daniel Gil, Pedro Gil Vicente and Luis-J. Saiz-Adalid. Abstract Con la continua reducción de tamaño de la tecnología CMOS, la probabilidad de sufrir tanto fallos simples como múltiples en los […]
Jul
15
Paper presented at ITACA-WIICT 2022 (II)
July 15, 2022 | Comments Off on Paper presented at ITACA-WIICT 2022 (II)
The paper entitled “Analysis of overheads caused by adding Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, P.Martín-Tabares, C. Martínez-Ruiz and L.J. Saiz-Adalid has been presented at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Jul
15
Paper presented at ITACA-WIICT 2022 (I)
July 15, 2022 | Comments Off on Paper presented at ITACA-WIICT 2022 (I)
The paper entitled “Tolerating Double and Triple Random Errors with Low Redundancy Error Correction Codes”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás and P.J. Gil-Vicente has been presented at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Jun
29
Paper accepted at ITACA-WIICT 2022 (II)
June 29, 2022 | Comments Off on Paper accepted at ITACA-WIICT 2022 (II)
The paper entitled “Analysis of overheads caused by adding Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, P.Martín-Tabares, C. Martínez-Ruiz and L.J. Saiz-Adalid has been accepted at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022). Abstract Nowadays, CMOS technology integration scale has allowed memory systems with a large storage capacity. […]