Jun
29
Paper accepted at ITACA-WIICT 2023 (II)
June 29, 2023 | | Comments Off on Paper accepted at ITACA-WIICT 2023 (II)
The paper entitled “Hardware Accelerating a Convolutional Neural Network Using High-Level Synthesis”, authored by David de Andrés and Juna Carlos Ruiz has been accepted at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023).
Abstract
Nowadays, the deployment of deep learning solutions at the edge in industrial, automotive, or medical environments, to cite a few, requires balancing different conflicting goals, like throughput, power consumption, silicon area, and robustness. Hence, the high throughput per watt of programmable-logic devices makes them suitable candidates to act as hardware accelerators for convolutional neural networks. However, it is a daunting task to model such networks at the register-transfer level, using a hardware description language, to implement them on the target technology efficiently. In recent years, high-level synthesis has provided an additional abstraction level, so hardware designers can focus on describing the behaviour of a system, and automated tools generate the detailed micro-architecture. This approach can reduce the cost of developing custom hardware accelerators for neural networks. Still, several parameters, compilation directives, and code transformations should be adequately applied to optimise the resulting implementation. This practical experience report presents a case study of a C description of a LeNet-5 convolutional neural network architecture and its adaptation to generate an optimised hardware implementation using high-level synthesis.
DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
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