Jul
10
Paper presented at ITACA-WIICT 2023 (II)
July 10, 2023 | Comments Off on Paper presented at ITACA-WIICT 2023 (II)
The paper entitled “Hardware Accelerating a Convolutional Neural Network Using High-Level Synthesis”, authored by David de Andrés and Juna Carlos Ruiz has been presented at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Jul
10
Paper presented at ITACA-WIICT 2023 (I)
July 10, 2023 | Comments Off on Paper presented at ITACA-WIICT 2023 (I)
The paper entitled “Comparison of the overheads provoked by the inclusion of different Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás, and P.J. Gil-Vicente has been presented at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Jun
29
Paper accepted at ITACA-WIICT 2023 (II)
June 29, 2023 | Comments Off on Paper accepted at ITACA-WIICT 2023 (II)
The paper entitled “Hardware Accelerating a Convolutional Neural Network Using High-Level Synthesis”, authored by David de Andrés and Juna Carlos Ruiz has been accepted at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023). Abstract Nowadays, the deployment of deep learning solutions at the edge in industrial, automotive, or medical environments, to cite […]
Jun
29
Paper accepted at ITACA-WIICT 2023 (I)
June 29, 2023 | Comments Off on Paper accepted at ITACA-WIICT 2023 (I)
The paper entitled “Comparison of the overheads provoked by the inclusion of different Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás, and P.J. Gil-Vicente has been accepted at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023). Abstract During these last years, the use of […]
Jun
29
Paper accepted at Jornadas SARTECO 2023 (III)
June 29, 2023 | Comments Off on Paper accepted at Jornadas SARTECO 2023 (III)
The paper entitled “Evaluación de la robustez de una red neuronal desarrollada para generar un acelerador HW” written by J.C. Ruiz-García, D. Andrés-Martínez and J. Gracia-Morán has been accepted at Jornadas SARTECO 2023. Abstract El uso combinado de lenguajes de programación de alto nivel con herramientas de automatización de diseño electrónico , facilita el desarrollo […]
Jun
29
Paper accepted at Jornadas SARTECO 2023 (II)
June 29, 2023 | Comments Off on Paper accepted at Jornadas SARTECO 2023 (II)
The paper entitled “Protección de comunicaciones entre vehículos autónomos mediante el uso de códigos de corrección de errores” written by J. Gracia-Morán, A. Vicente-García and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2023. Abstract La reducción de tamaño de la tecnología CMOS ha permitido aumentar las prestaciones de los sistemas empotrados. Sin embargo, esta […]
Jun
23
Paper accepted at Jornadas SARTECO 2023 (I)
June 23, 2023 | Comments Off on Paper accepted at Jornadas SARTECO 2023 (I)
The paper entitled “Uso de códigos de corrección de errores asimétricos en un sistema empotrado” written by J. Gracia-Morán, J.C. Ruiz-García and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2023. Abstract Durante estos últimos años, el desarrollo tecnológico ha propiciado un aumento en las prestaciones de los sistemas digitales, pero a costa de reducir […]
Nov
21
Paper accepted at DATE 2023
November 21, 2022 | Comments Off on Paper accepted at DATE 2023
The paper entitled “BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes”, authored by Ilya Tuzov, David de Andres, Juan-Carlos Ruiz and Carles Hernandez has been accepted at DATE 2023. Abstract FPGA-based fault injection (FFI) is an indispensable technique for verification and dependability assessment of FPGA designs and prototypes. Existing FFI tools […]
Oct
4
Paper presented at EDCC 2022
October 4, 2022 | Comments Off on Paper presented at EDCC 2022
David de Andrés has presented the paper entitled “Reversing FPGA architectures for speeding up fault injection: does it pay?” authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz at 18th European Dependable Computing Conference (EDCC 2022). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Sep
28
Presentation at Jornadas SARTECO 2022 (II)
September 28, 2022 | Comments Off on Presentation at Jornadas SARTECO 2022 (II)
Joaquín Gracia-Morán has presented the paper “Análisis del impacto de la inclusión de Códigos Correctores de Errores en un Sistema Empotrado basado en Arduino”, authored by Joaquín Gracia-Morán and Luis-J. Saiz-Adalid. Abstract El aumento en la escala de integración de los circuitos CMOS ha posibilitado la implementación de sistemas de memoria con una gran capacidad […]