Jun
27
Paper accepted at Jornadas SARTECO 2022 (I)
June 27, 2022 | Comments Off on Paper accepted at Jornadas SARTECO 2022 (I)
The paper entitled “Análisis del impacto de la inclusión de Códigos Correctores de Errores en un Sistema Empotrado basado en Arduino” written by J. Gracia-Morán and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2022. Abstract El aumento en la escala de integración de los circuitos CMOS ha posibilitado la implementación de sistemas de memoria […]
Jun
13
Paper accepted at EDCC 2022
June 13, 2022 | Comments Off on Paper accepted at EDCC 2022
The paper entitled “Reversing FPGA architectures for speeding up fault injection: does it pay?” authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz has been accepted at 18th European Dependable Computing Conference (EDCC 2022), that will be held in Zaragoza (Spain) from 12 to 15 of September. Abstract Although initially considered for fast system […]
Sep
17
DEFADAS project
September 17, 2021 | Comments Off on DEFADAS project
We have started our new project called DEFADAS, the acronym of “Dependable-enough FPGA-Accelerated DNNs for Automotive Systems” . Project research goals: Study the effect of faults on the different elements of FPGA-accelerated DNNs (convolution operators, pooling operators, fully connected layers, etc. implemented on LUTs, flip-flops, switch blocks, etc.), to define related fault models and failure […]