Jul
1
Attendance at Jornadas SARTECO
July 1, 2025 | Comments Off on Attendance at Jornadas SARTECO
Researchers from the Fault-Tolerant Systems Group participed in the last Josnadas SARTECO, that were held in Sevilla. During the event, the group’s researchers presented several oral communications focusing on advances from the national project the DEFADAS (Dependable-enough FPGA-Accelerated DNNs for Automotive Systems) and the project from the Universitat Politècnica de València (Convocatoria A+D, Proyectos de […]
Jun
2
Paper accepted at SAFECOMP 2025
June 2, 2025 | Comments Off on Paper accepted at SAFECOMP 2025
The paper entitled “Can C-Based ECC Models Leverage High-Level Synthesis? Evaluating Description Variants for Efficient Circuit Implementations”, authored by Joaquín Gracia-Morán, Juan-Carlos Ruiz, David de Andrés and Luis-J. Saiz-Adalid has been accepted at SAFECOMP 2025. Abstract: Error-Correcting Codes (ECCs) are essential for achieving fault tolerance in hardware accelerators deployed in safety-critical applications, such as those […]
Jul
2
Presentation at IFIP WG 10.4 meeting
July 2, 2024 | Comments Off on Presentation at IFIP WG 10.4 meeting
Juan C. Ruiz has presented the research work done by the Fault tolerant Systems research group of UPV at 86th IFIP WG 10.4 Meeting at Gold Coast, Australia, entitled “On improving the robustness of convolutional neural networks”.
Jun
28
IFIP WG 10.4 meeting
June 28, 2024 | Comments Off on IFIP WG 10.4 meeting
Juan C. Ruiz is attending the IFIP WG 10.4 meeting in Gold Coast, Australia. The IFIP WG 10.4 is aimed at identifying and integrating approaches, methods and techniques for specifying, designing, building, assessing, validating, operating and maintaining computer systems which should exhibit some or all of these attributes.
May
23
Paper available at IEEE early access
May 23, 2024 | Comments Off on Paper available at IEEE early access
The paper entitled “A Hybrid Technique based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM arrays”, written by Daniel Gil-Tomás, Luis J. Saiz-Adalid, Joaquín Gracia-Morán, J. Carlos Baraza-Calvo and Pedro J. Gil-Vicente is now available at IEEE Access. Abstract: MBU is an increasing challenge in SRAM memory, due to the chip’s […]
Jan
31
Paper accepted at EDCC 2024
January 31, 2024 | Comments Off on Paper accepted at EDCC 2024
The paper entitled “Zero-Space In-Weight and In-Bias Protection for Floating-Point-based CNNs”, written by Juan Carlos Ruiz, David de Andrés, Luis José Saiz-Adalid and Joaquín Gracia-Morán has been accepted at 19th European Dependable Computing Conference (EDCC), that will be held in Leuven (Belgium) next april. Abstract Deploying convolutional neural networks (CNNs) in image classification systems requires […]
Feb
13
Fault injection at ISOLDE Project
February 13, 2023 | Comments Off on Fault injection at ISOLDE Project
Juan Carlos Ruiz and David de Andrés will collaborate in the ISOLDE project (High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems), from the Horizon Europe Framework Programme (HORIZON). They will be responsible of different fault-injection tasks: – Bit accurate FPGA-fault injection tool with relevant fault-models development.– Bit accurate FPGA-fault injection tool adaptation to target […]
Sep
17
DEFADAS project
September 17, 2021 | Comments Off on DEFADAS project
We have started our new project called DEFADAS, the acronym of “Dependable-enough FPGA-Accelerated DNNs for Automotive Systems” . Project research goals: Study the effect of faults on the different elements of FPGA-accelerated DNNs (convolution operators, pooling operators, fully connected layers, etc. implemented on LUTs, flip-flops, switch blocks, etc.), to define related fault models and failure […]