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Keynote speech at EDCC 2022
September 5, 2022 | | Comments Off on Keynote speech at EDCC 2022
Juan Carlos Ruiz-García has been invited by the EDCC 2022 Steering Committe to give a Keynote Speech entitled “Reconfigurable logic for automotive edge computing: from promises to dependability assessment challenges”, inside the Critical Automotive applications: Robustness & Safety (CARS) workshop.
Abstract:
Reconfigurable logic devices have provided means to meet the requirements of evolution existing in parts of modern automotive embedded HW systems. The combination of hard (fast) and reconfigurable (flexible) logic, leads the promise of automotive-graded HW platforms enabling manufacturers to tailor accelerators to specific applications and models. In such a way, HW platforms can be customized attending to the needs of each embedded subsystem to provide higher levels of performance at lower levels of power consumption, and (re-)adjust parts of the logic attending to the set of safety requirements under consideration, existing threats, and their evolution along the time. Despite the high potential of this technology to produce more sophisticated automotive systems, its practical exploitation poses serious doubts in part due to the many challenges that must be addressed when assessing the robustness of the hardware running in the system reconfigurable logic. Although the ISO 26262 standard recommends the use of experimental fault injection for this type of assessment, the spatial and temporal complexity of the logic implementation and the various fault models to consider leads to very long injection campaigns that are unaffordable in practice. One solution is to decrease the level of detail of implementations and inject faults on high-level logic models. Another possibility consists in reducing the number of faults to inject to decrease the experimental time. Both solutions are largely used in the domain, but one must be aware about the existing implications on accuracy and representativity of results. This keynote speech explores this problem, identifying the challenges existing when dealing with experimental fault injection on reconfigurable logic and proposing some solutions to make this type of dependability assessment feasible.
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