Jun
29
Paper accepted at ITACA-WIICT 2022 (I)
June 29, 2022 | | Comments Off on Paper accepted at ITACA-WIICT 2022 (I)
The paper entitled “Tolerating Double and Triple Random Errors with Low Redundancy Error Correction Codes”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás and P.J. Gil-Vicente has been accepted at IX Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2022).
Abstract
With the continuous size reduction of CMOS technology, faults suffered by RAM memory systems are more likely. Thus, the probability of occurrence of Multiple Cell Upsets (MCUs), in addition to Single Cell Upsets (SCUs), augments. Traditionally, Error Correction Codes (ECCs) are a family of Fault Tolerance Mechanisms (FTMs) that have been used to protect memories. An aspect to consider when designing ECCs is the area, delay, and power consumption overheads that encoder and decoder circuits introduce, as well as the number of redundant bits used by the Error Correction Code.
In this work, we introduce a series of new low redundancy Error Correction Codes specially designed to correct multiple random errors. We have compared error coverage and overheads introduced by these new codes with other well-known ones. In this way, we have been able to study the influence of this low redundancy in the area, power consumption, and delay overheads.
DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
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