Jun
26
Invited speaker at DNS 2024
June 26, 2024 | Comments Off on Invited speaker at DNS 2024
This June 24, the VERDI workshop (co-located with DSN 2024) was held in Brisbane, Australia. In this workshop, Juan C. Ruiz has been the invited speaker with a talk entitled “On improving the robustness of convolutional neural networks using in-parameter zero-space error correction codes“. The program of VERDI 2024 can be seen here. This talk […]
Jun
26
Presentation at Jornadas SARTECO 2024 (III)
June 26, 2024 | Comments Off on Presentation at Jornadas SARTECO 2024 (III)
J.C. Ruiz-García has presented the paper entitled “Tolerancia a fallos múltiples en redes convolucionales en coma flotante de 16 bits utilizando códigos correctores de errores”, authored by J.C. Ruiz-García, D. de Andrés Martínez, Luis J. Saiz-Adalid and J. Gracia-Morán at Jornadas SARTECO 2024 in A Coruña.
Jun
26
Presentation at Jornadas SARTECO 2024 (II)
June 26, 2024 | Comments Off on Presentation at Jornadas SARTECO 2024 (II)
J. Gracia-Morán has presented the paper entitled “Protección mediante Códigos de Corrección de Errores de los pesos de una Red Neuronal implementada en Arduino”, authored by J. Gracia-Morán and Luis J. Saiz-Adalid at Jornadas SARTECO 2024 in A Coruña.
Jun
18
Presentation at Jornadas SARTECO 2024 (I)
June 18, 2024 | Comments Off on Presentation at Jornadas SARTECO 2024 (I)
Luis J. Saiz-Adalid has presented the paper entitled “Estudio de la confiabilidad de una red neuronal convolucional cuantizada”, authored by J. Gracia-Morán, Luis J. Saiz-Adalid, J.C. Ruiz-García, D. de Andrés Martínez at Jornadas SARTECO 2024 in A Coruña.
May
23
Paper available at IEEE early access
May 23, 2024 | Comments Off on Paper available at IEEE early access
The paper entitled “A Hybrid Technique based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM arrays”, written by Daniel Gil-Tomás, Luis J. Saiz-Adalid, Joaquín Gracia-Morán, J. Carlos Baraza-Calvo and Pedro J. Gil-Vicente is now available at IEEE Access. Abstract: MBU is an increasing challenge in SRAM memory, due to the chip’s […]
May
13
Paper accepted at IEEE Access
May 13, 2024 | Comments Off on Paper accepted at IEEE Access
The paper entitled “A Hybrid Technique based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM arrays”, written by Daniel Gil-Tomás, Luis J. Saiz-Adalid, Joaquín Gracia-Morán, J. Carlos Baraza-Calvo and Pedro J. Gil-Vicente has been accepted at IEEE Access. Abstract: MBU is an increasing challenge in SRAM memory, due to the chip’s […]
Apr
22
Paper accepted at SAFECOMP 2024
April 22, 2024 | Comments Off on Paper accepted at SAFECOMP 2024
The paper entitled “In-Memory Zero-Space Floating-Point-based CNN protection using non-significant and invariant bits”, and written by Juan Carlos Ruiz Garcia, Luis Jose Saiz-Adalid, David de Andrés Martínez, and Joaquín Gracia-Morán has been accepted at SAFECOMP 2024. Abstract Convolutional Neural Networks (CNNs) have accomplished significant success in various domains, including transportation, health care and banking. Millions […]
Apr
15
Paper accepted at Jornadas SARTECO 2024 (III)
April 15, 2024 | Comments Off on Paper accepted at Jornadas SARTECO 2024 (III)
The paper entitled “Tolerancia a fallos múltiples en redes convolucionales en coma flotante de 16 bitsutilizando códigos correctores de errores” written by J.C. Ruiz-García, D. Andrés-Martínez, L.J. Saiz-Adalid, and J. Gracia-Morán has been accepted at Jornadas SARTECO 2024. Abstract Multitud de sistemas utilizan redes convolucionales para identificar objetos en las imágenes que analizan. Este análisis […]
Apr
15
Paper accepted at Jornadas SARTECO 2024 (II)
April 15, 2024 | Comments Off on Paper accepted at Jornadas SARTECO 2024 (II)
The paper entitled “Estudio de la confiabilidad de una red neuronal convolucional cuantizada” written by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Ruiz-García, and D. Andrés-Martínez has been accepted at Jornadas SARTECO 2024. Abstract A medida que el uso de las redes neuronales se generaliza, el interés por su confiabilidad también aumenta. En concreto, las redes neuronales […]
Apr
15
Paper accepted at Jornadas SARTECO 2024 (I)
April 15, 2024 | Comments Off on Paper accepted at Jornadas SARTECO 2024 (I)
The paper entitled “Protección mediante Códigos de Corrección de Errores de los pesos de una Red Neuronal implementada en Arduino” written by J. Gracia-Morán and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2024. Abstract Últimamente, el amplio uso de las redes neuronales ha provocado que éstas estén presentes en multitud de entornos, como pueden […]