May
13
Paper accepted at IEEE Access
May 13, 2024 | Comments Off on Paper accepted at IEEE Access
The paper entitled “A Hybrid Technique based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM arrays”, written by Daniel Gil-Tomás, Luis J. Saiz-Adalid, Joaquín Gracia-Morán, J. Carlos Baraza-Calvo and Pedro J. Gil-Vicente has been accepted at IEEE Access. Abstract: MBU is an increasing challenge in SRAM memory, due to the chip’s […]
Apr
22
Paper accepted at SAFECOMP 2024
April 22, 2024 | Comments Off on Paper accepted at SAFECOMP 2024
The paper entitled “In-Memory Zero-Space Floating-Point-based CNN protection using non-significant and invariant bits”, and written by Juan Carlos Ruiz Garcia, Luis Jose Saiz-Adalid, David de Andrés Martínez, and Joaquín Gracia-Morán has been accepted at SAFECOMP 2024. Abstract Convolutional Neural Networks (CNNs) have accomplished significant success in various domains, including transportation, health care and banking. Millions […]
Apr
15
Paper accepted at Jornadas SARTECO 2024 (III)
April 15, 2024 | Comments Off on Paper accepted at Jornadas SARTECO 2024 (III)
The paper entitled “Tolerancia a fallos múltiples en redes convolucionales en coma flotante de 16 bitsutilizando códigos correctores de errores” written by J.C. Ruiz-García, D. Andrés-Martínez, L.J. Saiz-Adalid, and J. Gracia-Morán has been accepted at Jornadas SARTECO 2024. Abstract Multitud de sistemas utilizan redes convolucionales para identificar objetos en las imágenes que analizan. Este análisis […]
Apr
15
Paper accepted at Jornadas SARTECO 2024 (II)
April 15, 2024 | Comments Off on Paper accepted at Jornadas SARTECO 2024 (II)
The paper entitled “Estudio de la confiabilidad de una red neuronal convolucional cuantizada” written by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Ruiz-García, and D. Andrés-Martínez has been accepted at Jornadas SARTECO 2024. Abstract A medida que el uso de las redes neuronales se generaliza, el interés por su confiabilidad también aumenta. En concreto, las redes neuronales […]
Apr
15
Paper accepted at Jornadas SARTECO 2024 (I)
April 15, 2024 | Comments Off on Paper accepted at Jornadas SARTECO 2024 (I)
The paper entitled “Protección mediante Códigos de Corrección de Errores de los pesos de una Red Neuronal implementada en Arduino” written by J. Gracia-Morán and L.J. Saiz-Adalid has been accepted at Jornadas SARTECO 2024. Abstract Últimamente, el amplio uso de las redes neuronales ha provocado que éstas estén presentes en multitud de entornos, como pueden […]
Apr
13
Paper available at IEEE Latin American Transactions
April 13, 2024 | Comments Off on Paper available at IEEE Latin American Transactions
The paper entitled “A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words”, written by J. Gracia-Morán (ORCID), L. J. Saiz-Adalid (ORCID), J. C. Baraza-Calvo (ORCID), D. Gil-Tomás (ORCID) and P. J. Gil-Vicente (ORCID), can be accessed at IEEE Latin American Transactions. Video abstract here. Graphical abstract: Abstract Actual memory systems provide large […]
Mar
7
Paper accepted at IEEE Latin American Transactions
March 7, 2024 | Comments Off on Paper accepted at IEEE Latin American Transactions
The paper entitled “A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words”, written by J. Gracia-Morán (ORCID), L. J. Saiz-Adalid (ORCID), J. C. Baraza-Calvo (ORCID), D. Gil-Tomás (ORCID) and P. J. Gil-Vicente (ORCID), has been accepted at IEEE Latin American Transactions. Video Summary here Abstract Actual memory systems provide large storage capacity […]
Jan
31
Paper accepted at EDCC 2024
January 31, 2024 | Comments Off on Paper accepted at EDCC 2024
The paper entitled “Zero-Space In-Weight and In-Bias Protection for Floating-Point-based CNNs”, written by Juan Carlos Ruiz, David de Andrés, Luis José Saiz-Adalid and Joaquín Gracia-Morán has been accepted at 19th European Dependable Computing Conference (EDCC), that will be held in Leuven (Belgium) next april. Abstract Deploying convolutional neural networks (CNNs) in image classification systems requires […]
Jul
10
Paper presented at ITACA-WIICT 2023 (II)
July 10, 2023 | Comments Off on Paper presented at ITACA-WIICT 2023 (II)
The paper entitled “Hardware Accelerating a Convolutional Neural Network Using High-Level Synthesis”, authored by David de Andrés and Juna Carlos Ruiz has been presented at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033
Jul
10
Paper presented at ITACA-WIICT 2023 (I)
July 10, 2023 | Comments Off on Paper presented at ITACA-WIICT 2023 (I)
The paper entitled “Comparison of the overheads provoked by the inclusion of different Error Correction Codes in Embedded Systems”, authored by J. Gracia-Morán, L.J. Saiz-Adalid, J.C. Baraza-Calvo, D. Gil-Tomás, and P.J. Gil-Vicente has been presented at Workshop on Innovation on Information and Communication Technologies 2023 (ITACA-WIICT 2023). DEFADAS Project: Grant PID2020-120271RB-I00 funded by MCIN/AEI/10.13039/501100011033