• Search for:

• Recent Posts

  • Paper available at ACM
  • Paper accepted at LADC 2024
  • Paper available at Springer Link
  • 25th anniverary of Instituto ITACA
  • Presentation at IFIP WG 10.4 meeting

• Recent Comments

• Archives

  • December 2024
  • October 2024
  • July 2024
  • June 2024
  • May 2024
  • April 2024
  • March 2024
  • January 2024
  • September 2023
  • July 2023
  • June 2023
  • March 2023
  • February 2023
  • November 2022
  • October 2022
  • September 2022
  • July 2022
  • June 2022
  • May 2022
  • October 2021
  • September 2021
  • June 2021

The paper entitled “Allocating ECC parity bits into BF16-encoded CNN parameters: A practical experience report” written by Joaquín Gracia-Morán, Juan Carlos Ruiz Garcia, David de Andrés Martínez and Luis Jose Saiz-Adalid is available at ACM: https://dl.acm.org/doi/10.1145/3697090.3697092 Abstract Using low-precision data types, like the Brain Floating Point 16 (BF16) format, can reduce Convolutional Neural Networks (CNNs) […]

The paper entitled “Allocating ECC parity bits into BF16-encoded CNN parameters: A practical experience report” written by Joaquín Gracia-Morán, Juan Carlos Ruiz Garcia, David de Andrés Martínez and Luis Jose Saiz-Adalid has been accepted at 13th Latin-American Symposium on Dependable and Secure Computing (LADC 2024), that will be held in Recife (Brazil) next November. Abstract […]

The paper entitled “In-Memory Zero-Space Floating-Point-based CNN protection using non-significant and invariant bits”, and written by Juan Carlos Ruiz Garcia, Luis Jose Saiz-Adalid, David de Andrés Martínez, and Joaquín Gracia-Morán, published at SAFECOMP 2024, can be accesed at this link. Abstract Convolutional Neural Networks (CNNs) have accomplished significant success in various domains, including transportation, health […]

Juan C. Ruiz has presented the research work done by the Fault tolerant Systems research group of UPV at 86th IFIP WG 10.4 Meeting at Gold Coast, Australia, entitled “On improving the robustness of convolutional neural networks”.

Juan C. Ruiz, Luis J. Saiz and Joaquín Gracia have attended the CEDI 2024, that was held in A Coruña, Spain. During these days, they have contacted with others researches, exchanging ideas and establishing possible future collaborations

This June 24, the VERDI workshop (co-located with DSN 2024) was held in Brisbane, Australia. In this workshop, Juan C. Ruiz has been the invited speaker with a talk entitled “On improving the robustness of convolutional neural networks using in-parameter zero-space error correction codes“. The program of VERDI 2024 can be seen here. This talk […]

J.C. Ruiz-García has presented the paper entitled “Tolerancia a fallos múltiples en redes convolucionales en coma flotante de 16 bits utilizando códigos correctores de errores”, authored by J.C. Ruiz-García, D. de Andrés Martínez, Luis J. Saiz-Adalid and J. Gracia-Morán at Jornadas SARTECO 2024 in A Coruña.

J. Gracia-Morán has presented the paper entitled “Protección mediante Códigos de Corrección de Errores de los pesos de una Red Neuronal implementada en Arduino”, authored by J. Gracia-Morán and Luis J. Saiz-Adalid at Jornadas SARTECO 2024 in A Coruña.

Luis J. Saiz-Adalid has presented the paper entitled “Estudio de la confiabilidad de una red neuronal convolucional cuantizada”, authored by J. Gracia-Morán, Luis J. Saiz-Adalid, J.C. Ruiz-García, D. de Andrés Martínez at Jornadas SARTECO 2024 in A Coruña.

The paper entitled “A Hybrid Technique based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM arrays”, written by Daniel Gil-Tomás, Luis J. Saiz-Adalid, Joaquín Gracia-Morán, J. Carlos Baraza-Calvo and Pedro J. Gil-Vicente is now available at IEEE Access. Abstract: MBU is an increasing challenge in SRAM memory, due to the chip’s […]

keep looking »

• Categories

  • Congress
  • Congress Paper
  • DEFADAS
  • Journal Paper
  • Keynote
  • Meeting
  • Research
  • Teaching