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Juan C. Ruiz has presented the research work done by the Fault tolerant Systems research group of UPV at 86th IFIP WG 10.4 Meeting at Gold Coast, Australia, entitled “On improving the robustness of convolutional neural networks”.

Juan C. Ruiz, Luis J. Saiz and Joaquín Gracia have attended the CEDI 2024, that was held in A Coruña, Spain. During these days, they have contacted with others researches, exchanging ideas and establishing possible future collaborations

This June 24, the VERDI workshop (co-located with DSN 2024) was held in Brisbane, Australia. In this workshop, Juan C. Ruiz has been the invited speaker with a talk entitled “On improving the robustness of convolutional neural networks using in-parameter zero-space error correction codes“. The program of VERDI 2024 can be seen here. This talk […]

J.C. Ruiz-García has presented the paper entitled “Tolerancia a fallos múltiples en redes convolucionales en coma flotante de 16 bits utilizando códigos correctores de errores”, authored by J.C. Ruiz-García, D. de Andrés Martínez, Luis J. Saiz-Adalid and J. Gracia-Morán at Jornadas SARTECO 2024 in A Coruña.

J. Gracia-Morán has presented the paper entitled “Protección mediante Códigos de Corrección de Errores de los pesos de una Red Neuronal implementada en Arduino”, authored by J. Gracia-Morán and Luis J. Saiz-Adalid at Jornadas SARTECO 2024 in A Coruña.

Luis J. Saiz-Adalid has presented the paper entitled “Estudio de la confiabilidad de una red neuronal convolucional cuantizada”, authored by J. Gracia-Morán, Luis J. Saiz-Adalid, J.C. Ruiz-García, D. de Andrés Martínez at Jornadas SARTECO 2024 in A Coruña.

The paper entitled “A Hybrid Technique based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM arrays”, written by Daniel Gil-Tomás, Luis J. Saiz-Adalid, Joaquín Gracia-Morán, J. Carlos Baraza-Calvo and Pedro J. Gil-Vicente is now available at IEEE Access. Abstract: MBU is an increasing challenge in SRAM memory, due to the chip’s […]

The paper entitled “A Hybrid Technique based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM arrays”, written by Daniel Gil-Tomás, Luis J. Saiz-Adalid, Joaquín Gracia-Morán, J. Carlos Baraza-Calvo and Pedro J. Gil-Vicente has been accepted at IEEE Access. Abstract: MBU is an increasing challenge in SRAM memory, due to the chip’s […]

The paper entitled “In-Memory Zero-Space Floating-Point-based CNN protection using non-significant and invariant bits”, and written by Juan Carlos Ruiz Garcia, Luis Jose Saiz-Adalid, David de Andrés Martínez, and Joaquín Gracia-Morán has been accepted at SAFECOMP 2024. Abstract Convolutional Neural Networks (CNNs) have accomplished significant success in various domains, including transportation, health care and banking. Millions […]

The paper entitled “Tolerancia a fallos múltiples en redes convolucionales en coma flotante de 16 bitsutilizando códigos correctores de errores” written by J.C. Ruiz-García, D. Andrés-Martínez, L.J. Saiz-Adalid, and J. Gracia-Morán has been accepted at Jornadas SARTECO 2024. Abstract Multitud de sistemas utilizan redes convolucionales para identificar objetos en las imágenes que analizan. Este análisis […]

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